Any integer-based CPLD design of semi-integer frequency divider

In the digital system design, according to different design needs, we often encounter even frequency, odd-frequency, semi-integer frequency, etc., in some cases the duty cycle requirements. Based cpld (complex programmable logic device) digital system design, very easy to implement cascading from the counter or even create various forms of frequency and duty cycle such as the odd non-frequency, but the duty cycle, etc. the odd half-integer frequency division and frequency division of the more difficult to achieve.

In this paper, vhdl (very high speed integrated circuit hardware description language), by quartus ⅱ 4.2 development platform, designed to achieve such a duty cycle of the integer and duty cycle similar to other half-integer frequency divider, this design principle simple, and only a few cpld logic macrocell.

1 Design Principles

System block diagram shown in Figure 1.

Any integer-based CPLD design of semi-integer frequency divider

According to different frequency division factor to set the appropriate counter cycle count corresponding to each input clock signal fi of a cycle, so that q0 fi only the rising edge and generate an appropriate range of high count, and finally logical q0 and q1 or operation, and then get the required frequency signal fo. q1 is the role of complement in the odd frequency in half a clock cycle, the falling edge of Department, to other duty cycle and frequency in half-integer, in place to produce the falling edge of the clock frequency signal rising edge, in order to achieve half-integer frequency.

Here's how to determine the counter cycle, and q0, q1 produce high output range of each count. The narrative convenience, is as follows tag: frequency coefficient divide (max downto 0), where max is the frequency number corresponding to a binary number of the highest position, the half-integer frequency, the lowest level ie 0 for the decimal places; q 0_count and q1_count q0 and q1 respectively, produced a count of high range and note the divide (max downto 1) as a, divide (max downto 2) is b, divide (max downto 0) -1 for the c.

1.1 Even and odd frequency

Counter cycles from 0 to c. Even so the duty cycle frequency is very easy to implement, without any description of this. On the odd frequency, just as q0_count <a high output when q0, when q1_count = a-1 時(shí) output of a cycle of high q1, q0 and q1 other cases are as low, then q0 and q1 logic or obtained the required output fo is the base frequency clock signal.

Half-integer frequency 1.2

The counter cycles from 0 to c. If the integer part is even, just when q0_count <b q0 output when high, when b ≤ q1_count <a + b q1 output high when the other case, q0 and q1 are low; if the integer part is odd just when q0_coun ≤ b q0 output when high, when b ≤ q1_count ≤ a + b output is high, other cases are as low q0 and q1, q0 and q1 then the logic output or income that is required f0 half-integer frequency clock signal.

2 Simulation results and hardware circuits

Based on the above principles, developed using quartus ⅱ 4.2 7.5 7 frequency and frequency of the simulated waveform shown in Figure 2 and Figure 3.

Any integer-based CPLD design of semi-integer frequency divider

Any integer-based CPLD design of semi-integer frequency divider

Just slightly modify the program, you can achieve an arbitrary integer and half-integer frequency.

The design altera's epm7064slc84-10 form of a data acquisition system tested, good performance.

3 Conclusion

Sub-band method is simple, has some general, but also use fewer cpld logic macrocell, as in epm7064, the above simulation of the two dividers are only seven logic macrocell.