FPGA-based implementation of the fractional divider

Frequency synthesis is an important component of modern communications systems, he has a high stability and high accuracy reference frequency, after four operations produce the same degree of stability and the frequency of reference. Crossover is the most basic IC is also the most commonly used circuits. Integer frequency divider to achieve relatively simple, can use standard counters or programmable logic device design and implementation. However, in some cases, the clock source and not a multiple of the desired frequency relationship between the fractional divider can be used at this time divide. In this paper, the hardware description language design VerilogHDL way through ModelSimSE simulation software development, design FPGA-based dual-mode pre-decimal divider. With the development of ultra large scale integrated circuits using FPGA fractional synthesis technology to solve a single-loop digital frequency synthesizer phase of high frequency and small frequency interval between the conflicts.

1 Principle of dual-mode pre-fractional

Fractional divider implementation methods, but the same basic principle, that is, in a number of frequency cycles to take a certain approach allows certain period Multi meter a few dollars or less, counting cycle in the whole meaning of the overall average obtain a fractional frequency ratio, frequency setting to be the ratio of the fractional K, K can be expressed as:

FPGA-based implementation of the fractional divider

Type in: n, N, X are positive integers; n is the number of bits to X, that K has n decimal places. On the other hand, frequency division ratio can also be written:

FPGA-based implementation of the fractional divider

The formula: M is the number of input pulse divider; P for the output pulses.

FPGA-based implementation of the fractional divider

So P = 10n, then:

FPGA-based implementation of the fractional divider

These are the fractional divider of a realization that the N divider during 10n times when trying to multi-input X pulses.

2 circuit

Each cycle frequency N +10- nX, the circuit mode pre-decimal divider circuit by the ÷ N / N +1 divider mode, control counters and control logic of three parts. When a point level to 1, to ÷ N frequency; When a point level for the 0 to ÷ N +1 divider. Appropriate design control logic, so that the 10n divider sub-frequency cycle, with X times to ÷ N +1 frequency, so that when the output from the fo 10n a pulse, in fi, enter the X. (N +1) + (10n-X). N pulses, which is 10n.N + X pulses, the principle shown in Figure 1.

FPGA-based implementation of the fractional divider

3 Fractional Divider of Verilog-HDL design

Is through? Had to design a frequency divider factor of 8.7 to give the language used to design digital logic circuits VerilogHDL the general design. Used here ÷ 8 / 9 dual-modulus prescaler, in accordance with the preceding analysis, can be counted by the counter 3 times 8 frequency do first, then do 7 9 frequency, average frequency factor can be 8.7. As the switching frequency from N to N +1 N +1 frequency division and frequency division from the switch to the N frequency will increase over time to produce a phase shift, if a simple first 8 minutes, 3 times frequency of 9 points after 7 do will have a huge frequency phase fluctuations. Taking into account the fractional divider to divide many times 8 and 9 at frequency, then try to mix the two kinds of uniform frequency, this "uniform" is accomplished through the counter, where only a small number of discussions situation, the following brief this mixed approach:

Once for each frequency, frequency count is 10 minus the coefficient of fractional part, cumulative count of all times. If the cumulative result of less than 10, then for N +1 frequency, if more than 10 or equal to 10, while for N frequency. The case count was (10-7) = 3, 3 times before cumulative results are less than 10, so 9 frequency, cumulative results of the fourth 12, the cumulative results after removing 10 bits into 2 , same time 8 minutes frequency, Table 1 shows the frequency of the crossover process.

If the frequency factor for the two after the decimal, then use the 100 minus the fractional part of frequency coefficients. Using VerilogHDL design ÷ 8 / 9 prescaler dual description of procedures are as follows:

FPGA-based implementation of the fractional divider

4 Waveform Simulation

Above ÷ 8 / 9 dual-modulus prescaler ModelSim compiled by a description of procedures, timing simulation, the received waveform shown in Figure 2.

FPGA-based implementation of the fractional divider

Can be seen from Figure 2, when reset to 0, the divider reset, when a is 1, for 8 minutes frequency, when a is 0 to 9, then divide.

FPGA-based implementation of the fractional divider

Shown in Figure 3, the first three clocks, a value of 0, then the frequency to 9 points, followed by a clock a 1, for 8 minutes frequency, after the two pulses, but also for 9 frequency, time after 8, frequency, and then twice a 9 frequency, culminating in a frequency of 8 points.

5 circuit

FPGA Field Programmable Gate Array (FieldProgrammableGateArray) in the 20th century emerged in the mid 80's high-density programmable logic devices. FPGA and its software is the latest development of digital circuit technology. He used the EDA technology to circuit schematics, hardware description language, the form of state machine logic input design; he provides functional simulation, timing simulation and other simulation tools, in the functional simulation and timing simulation and satisfy the request, after a series of transformations, convert the input logic FPGA device programming files, in order to achieve specific integrated circuit. This design uses Xilinx Introduces the 90nm process manufacturing field programmable gate array Spartan-3 to design fractional divider, the volume decreases, more reliable.

6 Conclusion

Frequency divider design using pre-decimal divider, fractional divider counter the impact of controlled precision, when n is 100, the fractional precision of 1 / 100; when the n value of 1000 , fractional precision of 1 / 1000; and so forth. FPGA hardware resources are quite rich, so you can use the FPGA design high-precision decimal divider. Formed using FPGA digital frequency synthesizer, frequency of single-loop phase over 100MHz, resolution up to 10-6. Fractional divider that has been widely used, for example, the line image acquisition system frequency and column frequency design, it can be applied to the divider circuit as a clock generator.